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Appendix A Idealized RISC

The details provided in this appendix may assist interpretation of the example in Section 2 and the results presented in Section 4. FABIUS currently generates code for an idealized RISC machine that closely resembles the MIPS architecture. The primary difference is a lack of delay slots: memory access, branch, and call instructions require only one cycle to complete. The idealized RISC also supports a richer instruction set, including operations like move, push, and call; procedure linkage uses the stack.

The emit pseudo-instruction is interpreted by our RISC simulator rather than being expanded by the code generator, which facilitates the investigation of various peephole optimizations. The timings described in Section 4 attribute a cost of four cycles and a size of four words to most emit instructions. On the MIPS, two cycles would be required to load the 32-bit representation of a fixed-operand instruction into a register. Two additional cycles are required to store the instruction and update a code-segment pointer; the pointer update fills the delay slot of the store instruction. The cost of updating the pointer could be amortized over several emits, so we can reduce the average cost if another instruction is available to fill the delay slot. Fast allocation of code space is a critical requirement. We assume a garbage-collected code segment with amortized or hardware-supported overflow checking and cache flushing.

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